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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
CS_DEV
SCLK_PWR0
SDI_PWR1
GPO2_MOD
DI7
DO7
DI6
DO6
DI5
DO5
DI4
DO4
DI3
DO3
DI2
DO2
DI1
DO1
DI0
DO0
DI7
DO7
DI6
DO6
DI5
DO5
DI4
DO4
DI3
DO3
DI2
DO2
DI1
DO1
DI0
DO0
DATA 1
Figure 2. SPI Format
The following commands are implemented in the MAX7060:
DATA n
SPI Commands
Write: Within the same CS _DEV cycle, a write command is implemented as follows:
SDI_PWR1:
<0x01> <Initial Address> <Data 1> <Data 2> … <Data N>
With this command, Data 1 is written to the address given by <Initial Address>, Data 2 is written to <Initial Address +
1>, and so on.
Read: Within the same CS _DEV cycle, a read command is implemented as follows:
SDI_PWR1:
<0x02> <Address 1>
<Address 2>
<Address 3> … <Address N>
<0x00>
GPO2_MOD:
<0xXX>
<0xXX>
<Data 1>
<Data 2> … <Data N - 1>
<Data N>
With this command, all the registers can be read within the same cycle of CS _DEV. The addresses can be given in
any order.
CS_DEV
SCLK_PWR0
SDI_PWR1
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2 D1
D0
D7
D0
WRITE COMMAND (0x01)
INITIAL ADDRESS (A[7:0])
DATA 1
DATA N
Figure 3. SPI Write Command Format
16
Maxim Integrated
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